The present invention is related to systems and methods for clock management, and in particular to systems and methods for maintaining a desired clock frequency.
Phase lock loop circuits are used in many applications as frequency synthesizers to generate a precise frequency signal with both good phase noise and low spurs. An exemplary basic phase lock loop circuit is shown in FIG. 1, and may be used to manage clock frequency and phase. Turning to FIG. 1, a basic phase lock loop circuit 100 is shown that includes a phase/frequency detector 110, a charge pump 120, a loop filter 142 consisting of two capacitors 130, 150 and a resistor 140, a voltage controlled oscillator 160, and a frequency divider 170. In operation, a reference frequency 180 is compared with a divided feedback of an output frequency 190, and the comparison is used to drive voltage controlled oscillator 160 to form output frequency 190 consistent with reference frequency 180. Where frequency divider 170 causes a division by ‘N’, phase lock loop circuit 100 forces output frequency 190 to be exactly N times reference frequency 180. Phase/frequency detector 110 and charge pump 120 deliver either positive or negative charge pulses to voltage controlled oscillator 160 depending upon whether the phase of output frequency 180 leads or lags reference frequency 190. The delivered charge pulses are integrated by loop filter 142 to generate a tuning voltage (VVCO) that is applied to voltage controlled oscillator 160 causing the frequency to increase or decrease. As will be appreciated from the preceding description, output frequency 190 may be adjusted by changing either or both of reference frequency 180 or the value of frequency divider 170.
Even when phase lock loop circuit 100 is locked, charge pump 120 generates “spurs”. Loop filter 142 provides some reduction in such spurs before the spurs are visible to voltage controlled oscillator 160. Loop filter 142 includes a resistor 140 that provides a stability zero, and capacitor 130 suppresses glitches generated by charge pump 120 that occur in association with reference frequency comparison. In contrast, capacitor 150 operates to lower any ripple on the control voltage VVCO 143 applied to voltage controlled oscillator 160. However, capacitor 130 must typically be less than ten percent of the value of capacitor 150 to avoid under-damped settling. Thus, to assure sufficient reduction in ripple, phase lock loop circuit 100 requires a large value for capacitor 150 and an even larger value for capacitor 130. This, of course incurs all of the problems associated with using large capacitors including slow operation, and increased space requirements.
Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for clock management.